1. Field of the Invention
This invention is related to the field of processors and, more particularly, to the cancelling of speculative instructions in response to a branch misprediction.
2. Description of the Related Art
Branch instructions present numerous challenges to processor designers. The existence of branch instructions in code, and the mechanisms that the processor includes to handle the branch instructions with high performance, are frequently large factors in determining the overall performance that a user may actually experience when using a system including the processor.
One mechanism frequently used to address the challenges presented by branch instructions is speculative operation. Generally, branch instructions may be predicted (e.g. taken or not taken, for conditional branches, and/or branch target address predictions, for indirect branches and returns) and speculative operation may be performed based on the prediction. Instructions may be speculatively fetched and processed up to and/or including execution prior to resolution of the predicted branch instruction. If the prediction is correct, performance of the processor may be increased due to the speculative processing of the next instructions to be executed after the branch (either those at the branch target address or the sequential instructions). However, if the prediction is incorrect, the speculative instructions must be cancelled. Cancelling the speculative instructions, particularly in wide issue processors, may be complex.
A further difficulty introduced in some instruction set architectures (e.g. the MIPS instruction set architecture) involves the branch delay slot. The instruction in the branch delay slot is typically executed irrespective of whether the branch instruction is taken or not taken. However, for some branch instructions, the instruction in the branch delay slot is architecturally defined to be conditional based on whether the corresponding branch is taken or not taken. If the branch is taken, the instruction in the branch delay slot is executed. If the branch is not taken, the instruction in the branch delay slot is not executed. Thus, the branch delay slot instruction is treated differently for different branches, further complicating the cancelling of speculative instructions. Any type of instruction may be in the branch delay slot, and thus locating the instruction and cancelling or not cancelling the instruction based on which branch instruction that instruction follows is complicated.